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?2003 integrated device technology, inc. 1 november 2003 dsc-5632/3 ce 0r r/ w r ce 1r be 0r be 1r be 2r be 3r 256/128k x 36 memory array address decoder a 17r (1) a 0r address decoder ce 0l r/ w l ce 1l be 0l be 1l be 2l be 3l dout0-8_l dout9-17_l dout18-26_l dout27-35_l dout0-8_r dout9-17_r dout18-26_r dout27-35_r b e 0 l b e 1 l b e 2 l b e 3 l b e 3 r b e 2 r b e 1 r b e 0 r i/o 0l- i/o 35l a 17 l (1) a 0l i/o 0r - i/o 35r di n_l addr_l di n_r addr_r oe r oe l arbitration interrupt semaphore logic sem l int l (3) busy l (2 ,3) m/ s r/ w l oe l r/ w r oe r ce 0l ce 1l ce 0r ce 1r busy r (2,3) sem r int r (3) 4869 drw 01 zz cont rol logic zz l (4) zz r (4) jtag tc k trst tms tdi td o functional block diagram busy and interrupt flags on-chip port arbitration logic full on-chip hardware support of semaphore signaling between ports fully asynchronous operation from either port separate byte controls for multiplexed bus and bus matching compatibility sleep mode inputs on both ports supports jtag features compliant to ieee 1149.1 single 2.5v (100mv) power supply for core lvttl-compatible, selectable 3.3v (150mv)/2.5v (100mv) power supply for i/os and control signals on each port available in a 256-ball ball grid array, 208-pin plastic quad flatpack and 208-ball fine pitch ball grid array. industrial temperature range (?40c to +85c) is available for selected speeds features true dual-port memory cells which allow simultaneous access of the same memory location high-speed access ? commercial: 8/10/12/15ns (max.) ? industrial: 10/12ns (max.) rapidwrite mode simplifies high-speed consecutive write cycles dual chip enables allow for depth expansion without external logic idt70t651/9 easily expands data bus width to 72 bits or more using the master/slave select when cascading more than one device m/ s = v ih for busy output flag on master, m/ s = v il for busy input on slave high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram with 3.3v 0r 2.5v interface preliminary idt70t651/9s notes: 1. address a 17x is a nc for idt70t659. 2. busy is an input as a slave (m/ s =v il ) and an output when it is a master (m/ s =v ih ). 3. busy and int are non-tri-state totem-pole outputs (push-pull). 4. the sleep mode pin shuts off all dynamic inputs, except jtag inputs, when asserted. optx, int x, m/ s and the sleep mode pins themselves (zzx) are not affected during sleep mode.
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 2 description the idt70t651/9 is a high-speed 256/128k x 36 asynchronous dual-port static ram. the idt70t651/9 is designed to be used as a stand-alone 9216/4608k-bit dual-port ram or as a combination mas- ter/slave dual-port ram for 72-bit-or-more word system. using the idt master/slave dual-port ram approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. this device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by the chip enables (either ce 0 or ce 1 ) permit the on-chip circuitry of each port to enter a very low standby power mode. the idt70t651/9 has a rapidwrite mode which allows the designer to perform back-to-back write operations without pulsing the r/ w input each cycle. this is especially significant at the 8 and 10ns cycle times of the idt70t651/9, easing design considerations at these high perfor- mance levels. the 70t651/9 can support an operating voltage of either 3.3v or 2.5v on one or both ports, controlled by the opt pins. the power supply for the core of the device (v dd ) is at 2.5v.
3 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges pin configuration (1,2,3) notes: 1. all v dd pins must be connected to 2.5v power supply. 2. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v dd (2.5v), and 2.5v if opt pin for that port is set to v ss (0v). 3. all v ss pins must be connected to ground supply. 4. a 17 x is a nc for idt70t659. 5. package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 6. this package code is used to reference the package diagram. 70t651/9bc bc-256 (5,6) 256-pin bga top view e16 i/o 14r d16 i/o 16r c16 i/o 16l b16 nc a16 nc a15 nc b15 i/o 17l c15 i/o 17r d15 i/o 15l e15 i/o 14l e14 i/o 13l d14 i/o 15r d13 v dd c12 a 6l c14 opt l b14 nc a14 a 0l a12 a 5l b12 a 4l c11 busy l d12 v ddqr d11 v ddqr c10 sem l b11 nc a11 int l d8 v ddqr c8 be 1l a9 ce 1l d9 v ddql c9 be 0l b9 ce 0l d10 v ddql c7 a 7l b8 be 3l a8 be 2l b13 a 1l a13 a 2l a10 oe l d7 v ddqr b7 a 9l a7 a 8l b6 a 12l c6 a 10l d6 v ddql a5 a 14l b5 a 15l c5 a 13l d5 v ddql a4 a 17l (4) b4 nc c4 a 16l d4 v dd a3 nc b3 tdo c3 v ss d3 i/o 20l d2 i/o 19r c2 i/o 19l b2 nc a2 tdi a1 nc b1 i/o 18l c1 i/o 18r d1 i/o 20r e1 i/o 21r e2 i/o 21l e3 i/o 22l e4 v ddql f1 i/o 23l f2 i/o 22r f3 i/o 23r f4 v ddql g1 i/o 24r g2 i/o 24l g3 i/o 25l g4 v ddqr h1 i/o 26l h2 i/o 25r h3 i/o 26r h4 v ddqr j1 i/o 27l j2 i/o 28r j3 i/o 27r j4 v ddql k1 i/o 29r k2 i/o 29l k3 i/o 28l k4 v ddql l1 i/o 30l l2 i/o 31r l3 i/o 30r l4 v ddqr m1 i/o 32r m2 i/o 32l m3 i/o 31l m4 v ddqr n1 i/o 33l n2 i/o 34r n3 i/o 33r n4 v dd p1 i/o 35r p2 i/o 34l p3 tms p4 a 16r r1 i/o 35l r2 nc r3 trst r4 nc t1 nc t2 tck t3 nc t4 a 17r (4) p5 a 13r r5 a 15r p12 a 6r p8 be 1r p9 be 0r r8 be 3r t8 be 2r p10 sem r t11 int r p11 busy r r12 a 4r t12 a 5r p13 a 3r p7 a 7r r13 a 1r t13 a 2r r6 a 12r t5 a 14r t14 a 0r r14 opt r p14 i/o 0l p15 i/o 0r r15 nc t15 nc t16 nc r16 nc p16 i/o 1l n16 i/o 2r n15 i/o 1r n14 i/o 2l m16 i/o 4l m15 i/o 3l m14 i/o 3r l16 i/o 5r l15 i/o 4r l14 i/o 5l k16 i/o 7l k15 i/o 6l k14 i/o 6r j16 i/o 8l j15 i/o 7r j14 i/o 8r h16 i/o 10r h15 io 9l h14 i/o 9r g16 i/o 11r g15 i/o 11l g14 i/o 10l f16 i/o 12l f14 i/o 12r f15 i/o 13r r9 ce 0r r11 m/ s t6 a 11r t9 ce 1r a6 a 11l b10 r/ w l c13 a 3l p6 a 10r r10 r/ w r r7 a 9r t10 oe r t7 a 8r , e5 v dd e6 v dd e7 v ss e8 v ss e9 v ss e10 v ss e11 v dd e12 v dd e13 v ddqr f5 v dd f6 nc f8 v ss f9 v ss f10 v ss f12 v dd f13 v ddqr g5 v ss g6 v ss g7 v ss g8 v ss g9 v ss g10 v ss g11 v ss g12 v ss g13 v ddql h5 v ss h6 v ss h7 v ss h8 v ss h9 v ss h10 v ss h11 v ss h12 v ss h13 v ddql j5 zz r j6 v ss j7 v ss j8 v ss j9 v ss j10 v ss j11 v ss j12 zz l j13 v ddqr k5 v ss k6 v ss k7 v ss k8 v ss l5 v dd l6 nc l7 v ss l8 v ss m5 v dd m6 v dd m7 v ss m8 v ss n5 v ddqr n6 v ddqr n7 v ddql n8 v ddql k9 v ss k10 v ss k11 v ss k12 v ss l9 v ss l10 v ss l11 v ss l12 v dd m9 v ss m10 v ss m11 v dd m12 v dd n9 v ddqr n10 v ddqr n11 v ddql n12 v ddql k13 v ddqr l13 v ddql m13 v ddql n13 v dd f7 v ss f11 v ss 5632 drw 02f , 03/18/03
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 4 notes: 1. all v dd pins must be connected to 2.5v power supply. 2 . all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v dd (2.5v) and 2.5v if opt pin for that port is set to v ss (0v). 3. all v ss pins must be connected to ground. 4. a 17 x is a nc for idt70t659. 5. package body is approximately 28mm x 28mm x 3.5mm. 6. this package code is used to reference the package diagram. 7. 8ns commercial and 10ns industrial speed grades are not available in the dr-208 package. 8. this text does not indicate orientation of the actual part-marking. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 1 0 1 1 0 2 1 0 3 1 0 4 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 2 0 8 2 0 7 2 0 6 2 0 5 2 0 4 2 0 3 2 0 2 2 0 1 2 0 0 1 9 9 1 9 8 1 9 7 1 9 6 1 9 5 1 9 4 1 9 3 1 9 2 1 9 1 1 9 0 1 8 9 1 8 8 1 8 7 1 8 6 1 8 5 1 8 4 1 8 3 1 8 2 1 8 1 1 8 0 1 7 9 1 7 8 1 7 7 1 7 6 1 7 5 1 7 4 1 7 3 1 7 2 1 7 1 1 7 0 1 6 9 1 6 8 1 6 7 1 6 6 1 6 5 1 6 4 1 6 3 1 6 2 1 6 1 1 6 0 1 5 9 1 5 8 1 5 7 70t651/9dr dr-208 (5,6,7) 208-pin pqfp top view (8) i/o 19l i/o 19r i/o 20l i/o 20r v ddql v ss i/o 21l i/o 21r i/o 22l i/o 22r v ddqr v ss i/o 23l i/o 23r i/o 24l i/o 24r v ddql v ss i/o 25l i/o 25r i/o 26l i/o 26r v ddqr zz r v dd v dd v ss v ss v ddql v ss i/o 27r i/o 27l i/o 28r i/o 28l v ddqr v ss i/o 29r i/o 29l i/o 30r i/o 30l v ddql v ss i/o 31r i/o 31l i/o 32r i/o 32l v ddqr v ss i/o 33r i/o 33l i/o 34r i/o 34l v s s v d d q l i / o 3 5 r i / o 3 5 l v d d t m s t c k t r s t n c n c a 1 7 r ( 4 ) a 1 6 r a 1 5 r a 1 4 r a 1 3 r a 1 2 r a 1 1 r a 1 0 r a 9 r a 8 r a 7 r b e 3 r b e 2 r b e 1 r b e 0 r c e 1 r c e 0 r v d d v d d v s s v s s s e m r o e r r / w r b u s y r i n t r m / s a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 r v d d v s s v s s o p t r i / o 0 l i / o 0 r v d d q l v s s i/o 16l i/o 16r i/o 15l i/o 15r v ss v ddql i/o 14l i/o 14r i/o 13l i/o 13r v ss v ddqr i/o 12l i/o 12r i/o 11l i/o 11r v ss v ddql i/o 10l i/o 10r i/o 9l i/o 9r v ss v ddqr v dd v dd v ss v ss zz l v ddql i/o 8r i/o 8l i/o 7r i/o 7l v ss v ddqr i/o 6r i/o 6l i/o 5r i/o 5l v ss v ddql i/o 4r i/o 4l i/o 3r i/o 3l v ss v ddqr i/o 2r i/o 2l i/o 1r i/o 1l v s s v d d q r i / o 1 8 r i / o 1 8 l v s s v d d t d i t d o n c n c a 1 7 l ( 4 ) a 1 6 l a 1 5 l a 1 4 l a 1 3 l a 1 2 l a 1 1 l a 1 0 l a 9 l a 8 l a 7 l b e 3 l b e 2 l b e 1 l b e 0 l c e 1 l c e 0 l v d d v d d v s s v s s s e m l o e l r / w l b u s y l i n t l n c a 6 l a 5 l a 4 l a 3 l a 2 l a 1 l a 0 l v d d v d d v s s o p t l i / o 1 7 l i / o 1 7 r v d d q r v s s 5632 drw 02d 03/18/03 pin configurations (1,2,3) (con't.)
5 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges pin configurations (1,2,3) (con't.) notes: 1. all v dd pins must be connected to 2.5v power supply. 2 . all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v dd (2.5v) and 2.5v if opt pin for that port is set to v ss (0v). 3. all v ss pins must be connected to ground. 4. a 17 x is a nc for idt70t659. 5. package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 6. this package code is used to reference the package diagram. 7. this text does not indicate orientation of the actual part-marking. 17 16 15 14 12 13 10 9 8 7 6 5 4 3 2 1 11 a b c d e f g h j k l m n p r t u i/o 19l i/o 18l v ss a4 l int l sem l be 1l a 8l a 12l a 16l v ss i/o 17l opt l a 0l i/o 20r v ss i/o 18r nc a 1l a5 l busy l v ss ce 0l ce 1l be 2l a 9l a 13l a 17l (4) i/o16l v dd qr v ss v dd ql i/o 19 r v dd qr v dd a 2l a6 l r/ w l v ss be 3l a 10l a 14 l nc i/o 15l i/o 16r v dd i/o 22l v ss i/o 21l i/o 20l v dd a 3 l nc oe l i/o 23l i/o 22 r v ddqr i/o 21r v dd ql i/o 23r i/o 24l v ss i/o 26l v ss i/o 25l i/o 24r v dd i/o 26r v dd qr i/o 25r v dd ql v dd v ss zz r i/o 29r i/o 28 l v ddqr v dd ql i/o 29l i/o 30r v ss i/o 14r v ddql i/o 14l a 15l a 11l a 7l be 0l i/o 12l i/o 13r v ss i/o 13l v ss i/o 12r i/o 11l i/o 9l v ddql i/o 10l i/o 11r v dd i/o 9r v ss i/o 10r zz l v ddqr i/o 7r v ddql i/o8r v ss i/o 8l v ss i/o 7l i/o 6r a 0r a 1r a 2r a 3r a 4r a 5r a 6r i/o 3r i/o 31l v ss i/o 31r i/o 30l a 16r a 12r a 8r be 1r v dd sem r int r v ddqr i/o 2l i/o 3l i/o 4l v ss i/o 33l i/o 34r nc a 13r a 9r be 2r ce 0 r ce 1r v dd v ss busy r v ss v dd v ss v ddql i/o 1r v dd qr i/o 33r i/o 34l v ddql nc a 17r (4) a 14r a 10r be 3r v ss i/o 4r i/o 6l v ss i/o 5r i/o 2r v ss i/o 35l v dd a 15r a 11r a 7r be 0r oe r m/ s r/ w r v ddql i/o 5l opt r i/o 0l i/o 1l 70t651/9bf bf-208 (5,6) 208-ball fpbga top view (7) 5632 drw 02e i/o 27l i/o 28r v ss i/o 27r v ss i/o 32r i/o 32l v ddqr i/o 35r a b c d e f g h j k l m n p r t u v ss i/o 0r i/o 17r v ddqr v ss v dd v ss i/o 15r v dd v dd tdo tdi tck tms trst v ss 03/18/03
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 6 pin names notes: 1. address a 17 x is a nc for idt70t659. 2. v dd , opt x , and v ddqx must be set to appropriate operating levels prior to applying inputs on i/o x . 3. opt x selects the operating voltage levels for the i/os and controls on that port. if opt x is set to v dd (2.5v), then that port's i/os and controls will operate at 3.3v levels and v ddqx must be supplied at 3.3v. if opt x is set to v ss (0v), then that port's i/os and controls will operate at 2.5v levels and v ddqx must be supplied at 2.5v. the opt pins are independent of one another?both ports can operate at 3.3v levels, both can operate at 2.5v levels, or either can operate at 3.3v with the other at 2.5v. 4. the sleep mode pin shuts off all dynamic inputs, except jtag inputs, when asserted. optx, int x, m/ s and the sleep mode pins themselves (zzx) are not affected during sleep mode. it is recommended that boundry scan not be operated during sleep mode. 5. busy is an input as a slave (m/ s =v il ) and an output when it is a master (m/ s =v ih ). left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables (input) r/ w l r/ w r read/write enable (input) oe l oe r output enable (input) a 0l - a 17l (1) a 0r - a 17r (1) address (input) i/o 0l - i/o 35l i/o 0r - i/o 35r data input/output sem l sem r semaphore enable (input) int l int r interrupt flag (output) busy l busy r busy flag (output) be 0l - be 3l be 0r - be 3r byte enables (9-bit bytes) (input) v ddql v ddqr power (i/o bus) (3.3v or 2.5v) (2) (input) opt l opt r option for selecting v ddqx (2,3) (input) zz l zz r sleep mode pin (4) (input) m/ s master or slave select (input) (5) v dd power (2.5v) (2) (input) v ss ground (0v) (input) tdi test data input tdo test data output tck test logic clock (10mhz) (input) tms test mode select (input) trst reset (initialize tap controller) (input) 5632 tbl 01
7 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. it is possible to read or write any combination of bytes during a given access. a few representative samples have been illust rated here. truth table i?read/write and enable control (1,2) oe sem ce 0 ce 1 be 3 be 2 be 1 be 0 r/ w zz byte 3 i/o 27-35 byte 2 i/o 18-26 byte 1 i/o 9-1 7 byte 0 i/o 0-8 mode x h h x x x x x x l high-z high-z high-z high-z deselected?power down x h x l x x x x x l high-z high-z high-z high-z deselected?power down x h l h h h h h x l high-z high-z high-z high-z all bytes deselected x h l h h h h l l l high-z high-z high-z d in write to byte 0 only x h l h h h l h l l hig h-z hig h-z d in high-z write to byte 1 only xhl hhl hhl lhigh-z d in high-z high-z write to byte 2 only xhlhlhhhll d in high-z high-z high-z write to byte 3 only x h l h h h l l l l hig h-z hig h-z d in d in write to lower 2 bytes only xhlhllhhll d in d in high-z high-z write to upper 2 bytes only xhlhllllll d in d in d in d in write to all bytes l h l h h h h l h l high-z high-z high-z d out read byte 0 only lhlhhhlhhlhigh-zhigh-z d out high-z read byte 1 only lhlhhlhhhlhigh-z d out high-z high-z read byte 2 only lhlhlhhhhl d out high-z high-z high-z read byte 3 only lhlhhhllhlhigh-zhigh-z d out d out read lower 2 bytes only lhlhllhhhl d out d out high-z high-z read upper 2 bytes only lhlhllllhl d out d out d out d out read all bytes h h l h l l l l x l high-z high-z high-z high-z outputs disabled x x x x x x x x x h high-z high-z high-z high-z high-z sleep mode 5632 tbl 02 truth table ii ? semaphore read/write control (1) notes: 1. there are eight semaphore flags written to i/o 0 and read from all the i/os (i/o 0 -i/o 35 ). these eight semaphore flags are addressed by a 0 -a 2 . 2. ce = l occurs when ce 0 = v il and ce 1 = v ih . ce = h when ce 0 = v ih and/or ce 1 = v il . 3. each byte is controlled by the respective be n. to read data be n = v il . inputs (1 ) outputs mode ce (2 ) r/ w oe be 3 be 2 be 1 be 0 sem i/o 1-3 5 i/o 0 hhlllll ldata out data out read data in semaphore flag (3) h xxxxl l x data in write i/o 0 into semaphore flag lxxxxxx l ______ ______ not allowed 5632 tbl 03
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 8 recommended operating temperature and supply voltage (1) note: 1. this is the parameter ta. this is the "instant on" case temperature. grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v2.5v + 100mv industrial -40 o c to +85 o c0v2.5v + 100mv 5632 tbl 04 notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o . capacitance (1) (t a = +25c, f = 1.0mh z ) pqfp only symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 8 pf c out (3) output capacitance v out = 3dv 10.5 pf 5632 tbl 08 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this is a steady-state dc parameter that applies after the power supply has reached its nominal operating value. power sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 3. ambient temperature under dc bias. no ac conditions. chip deselected. recommended dc operating conditions with v ddq at 2.5v symbol parameter min. typ. max. unit v dd core supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage (3) 2.4 2.5 2.6 v v ss ground 0 0 0 v v ih input high volltage (address, control & data i/o inp uts) (3) 1.7 ____ v ddq + 100mv (2) v v ih input high voltage _ jtag 1.7 ____ v dd + 100mv (2) v v ih input high voltage - zz, op t, m/ s v dd - 0.2v ____ v dd + 100mv (2) v v il input low voltage -0.3 (1) ____ 0.7 v v il input low voltage - zz, op t, m/ s -0.3 (1) ____ 0.2 v 5632 tbl 05 notes: 1. v il (min.) = -1.0v for pulse width less than t rc /2 or 5ns, whichever is less. 2. v ih (max.) = v ddq + 1.0v for pulse width less than t rc /2 or 5ns, whichever is less. 3. to select operation at 2.5v levels on the i/os and controls of a given port, the opt pin for that port must be set to v ss (0v), and v ddqx for that port must be supplied as indicated above. absolute maximum ratings (1) symbol rating commercial & industrial unit v te rm (v dd ) v dd terminal voltage with respect to gnd -0.5 to 3.6 v v te rm (2 ) (v ddq ) v ddq terminal voltage with respect to gnd -0.3 to v ddq + 0.3 v v term (2) (inputs and i/o's) input and i/o terminal voltage with respect to gnd -0.3 to v ddq + 0.3 v t bias (3) temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out (for v ddq = 3.3v) dc output current 50 ma i out (for v ddq = 2.5v) dc output current 40 ma 5632 tbl 07 notes: 1. v il (min.) = -1.0v for pulse width less than t rc /2 or 5ns, whichever is less. 2. v ih (max.) = v ddq + 1.0v for pulse width less than t rc /2 or 5ns, whichever is less. 3. to select operation at 3.3v levels on the i/os and controls of a given port, the opt pin for that port must be set to v dd (2.5v), and v ddqx for that port must be supplied as indicated above. recommended dc operating conditions with v ddq at 3.3v symbol parameter min. typ. max. unit v dd core supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage (3) 3.15 3.3 3.45 v v ss ground 0 0 0 v v ih input high voltag e (address, control &data i/o inputs) (3) 2.0 ____ v ddq + 150mv (2) v v ih input high voltag e _ jtag 1.7 ____ v dd + 100mv (2) v v ih input high voltage - zz, op t, m/ s v dd - 0.2v ____ v dd + 100mv (2) v v il input low voltage -0.3 (1) ____ 0.8 v v il input lo w voltag e - zz, op t, m/ s -0.3 (1) ____ 0.2 v 5632 tbl 06
9 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges dc electrical characteristics over the operating temperature and supply voltage range (v dd = 2.5v 100mv) notes: 1. v ddq is selectable (3.3v/2.5v) via opt pins. refer to page 6 for details. 2. applicable only for tms, tdi and trst inputs. 3. outputs tested in tri-state mode. dc electrical characteristics over the operating temperature and supply voltage range (3) (v dd = 2.5v 100mv) notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc , using "ac test conditions" at input levels of gnd to 3.3v. 2. f = 0 means no address or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 3.3v, t a = 25c for typ, and are not production tested. i dd dc (f=0) = 100ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v ddqx - 0.2v ce x > v ddqx - 0.2v means ce 0x > v ddqx - 0.2v or ce 1x < 0.2v. "x" represents "l" for left port or "r" for right port. 6. i sb 1 , i sb 2 and i sb 4 will all reach full standby levels (i sb 3 ) on the appropriate port(s) if zz l and /or zz r = v ih . 7. 8ns commercial and 10ns industrial speed grades are available in bf-208 and bc-256 packages only. 70t651/9s8 (7) com'l only 70t651/9s10 com'l & ind (7) 70t651/9s12 com'l & ind 70t651/9s15 com'l only symbol parameter test condition version typ. (4) max. typ. (4) max. typ. (4) max. typ. (4) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled f = f max (1) com'l s 350 475 300 405 300 355 225 305 ma ind s ____ ____ 300 445 300 395 ____ ____ i sb1 (6) standby current (both ports - ttl level inputs) ce l = ce r = v ih f = f max (1) com'l s 115 140 90 120 75 105 60 85 ma ind s ____ ____ 90 145 75 130 ____ ____ i sb2 (6) standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f = f max (1) com'l s 240 315 200 265 180 230 150 200 ma ind s ____ ____ 200 290 180 255 ____ ____ i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v dd - 0.2v, v in > v dd - 0.2v or v in < 0.2v, f = 0 (2) com'ls210210210210 ma ind s ____ ____ 220220 ____ ____ i sb4 (6) full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v dd - 0.2v (5) v in > v dd - 0.2v or v in < 0.2v, active port, outputs disabled, f = f max (1) com'l s 240 315 200 265 180 230 150 200 ma ind s ____ ____ 200 290 180 255 ____ ____ i zz sleep mode current (both ports - ttl level inputs) zz l = zz r = v ih f = f max (1) com'ls210210210210 ma ind s ____ ____ 220220 ____ ____ 5632 tbl 10 symbol parameter test conditions 70t651/9s unit min. max. |i li | input leakage current (1) v ddq = max., v in = 0v to v ddq ___ 10 a |i li | jtag & zz input leakage current (1,2) v dd = max. , v in = 0v to v dd ___ + 30 a |i lo | output leakage current (1,3) ce 0 = v ih or ce 1 = v il , v out = 0v to v ddq ___ 10 a v ol (3.3v) output low voltage (1) i ol = +4ma, v ddq = min. ___ 0.4 v v oh (3.3v) output high voltage (1) i oh = -4ma, v ddq = min. 2.4 ___ v v ol (2.5v) output low voltage (1) i ol = +2ma, v ddq = min. ___ 0.4 v v oh (2.5v) output high voltage (1) i oh = -2ma, v ddq = min. 2.0 ___ v 5632 tbl 09
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 10 ac test conditions (v ddq - 3.3v/2.5v) input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v / gnd to 2.4v 2ns max. 1.5v/1.25v 1.5v/1.25v figure 1 5632 tbl 11 figure 1. ac output test load. 1.5v/1.25 50 ? 50 ? 5632 drw 03 10pf (tester) data out , 5632 drw 05 20 40 60 80 100 120 140 0 160 0 0.5 1 1.5 2 2.5 3 3.5 4 ? capacitance (pf) from ac test load ? t aa / t ace (typical, ns) figure 3. typical output derating (lumped capacitive load).
11 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges ac electrical characteristics over the operating temperature and supply voltage range (4) notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 1). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . either condition must be valid for the entire t ew time. ce = v il when ce 0 = v il and ce 1 = v ih . ce = v ih when ce 0 = v ih and/or ce 1 = v il . 4. these values are valid regardless of the power supply level selected for i/o and control signals (3.3v/2.5v). see page 6 for details. 5. 8ns commercial and 10ns industrial speed grades are available in bf-208 and bc-256 packages only. ac electrical characteristics over the operating temperature and supply voltage (4) symbol parameter 70t651/9s8 (5) com'l only 70t651/9s10 com'l & ind (5) 70t651/9s12 com'l & ind 70t651/9s15 com'l only unit min. max. min. max. min. max. min. max. read cycle t rc re ad cycle time 8 ____ 10 ____ 12 ____ 15 ____ ns t aa address access time ____ 8 ____ 10 ____ 12 ____ 15 ns t ace chip enable access time (3) ____ 8 ____ 10 ____ 12 ____ 15 ns t abe byte enable access time (3) ____ 4 ____ 5 ____ 6 ____ 7ns t aoe outp ut enab le acce ss time ____ 4 ____ 5 ____ 6 ____ 7ns t oh output hold from address change 3 ____ 3 ____ 3 ____ 3 ____ ns t lz output low-z time chip enable and semaphore (1,2) 3 ____ 3 ____ 3 ____ 3 ____ ns t lzob output low-z time output enable and byte enable (1,2) 0 ____ 0 ____ 0 ____ 0 ____ ns t hz output high-z time (1,2) 03.5040608ns t pu chip enab le to po we r up time (2) 0 ____ 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2) ____ 7 ____ 8 ____ 8 ____ 12 ns t sop semaphore flag update pulse ( oe or sem ) ____ 4 ____ 4 ____ 6 ____ 8ns t saa semaphore address access time 2 8 2 10 2 12 2 15 ns t soe semaphore output enable access time ____ 5 ____ 5 ____ 6 ____ 7ns 5632tbl 12 symbol parameter 70t651/9s8 (5) com'l only 70t651/9s10 com'l & ind (5) 70t651/9s12 com'l & ind 70t651/9s15 com'l only unit min. max. min. max. min. max. min. max. write cycle t wc write cycle time 8 ____ 10 ____ 12 ____ 15 ____ ns t ew chip enable to end-of-write (3) 6 ____ 7 ____ 9 ____ 12 ____ ns t aw address valid to end-of-write 6 ____ 7 ____ 9 ____ 12 ____ ns t as address set-up time (3) 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 6 ____ 7 ____ 9 ____ 12 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 4 ____ 5 ____ 7 ____ 10 ____ ns t dh data ho ld time 0 ____ 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 3.5 ____ 4 ____ 6 ____ 8ns t ow outp ut active fro m end-o f-write (1,2) 3 ____ 3 ____ 3 ____ 3 ____ ns t swrd sem flag write to read time 4 ____ 5 ____ 5 ____ 5 ____ ns t sps sem flag contention window 4 ____ 5 ____ 5 ____ 5 ____ ns 5632 tbl 13
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 12 timing of power-up power-down waveform of read cycles (5) notes: 1. timing depends on which signal is asserted last, oe , ce or be n. 2. timing depends on which signal is de-asserted first ce , oe or be n. 3. t bdd delay is required only in cases where the opposite port is completing a write operation to the same address location. for simu ltaneous read operations busy has no relation to valid output data. 4. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa , t abe or t bdd . 5. sem = v ih . 6. ce = l occurs when ce 0 = v il and ce 1 = v ih . ce = h when ce 0 = v ih and/or ce 1 = v il . t rc r/ w ce addr t aa oe be n 5632 drw 06 (4) t ace (4) t aoe (4) t abe (4) (1) t lz /t lzob t oh (2) t hz (3,4) t bdd data out busy out valid data (4) (6) . ce 5632 drw 07 t pu i cc i sb t pd 50% 50% .
13 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges timing waveform of write cycle no. 1, r/ w controlled timing (1,5,8) timing waveform of write cycle no. 2, ce controlled timing (1,5,8) notes: 1. r/ w or ce or be n = v ih during all address transitions for write cycles 1 and 2. 2. a write occurs during the overlap (t ew or t wp ) of a ce = v il, be n = v il , and a r/ w = v il for memory array writing cycle. 3. t wr is measured from the earlier of ce , be n or r/ w (or sem or r/ w ) going high to the end of write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or sem = v il transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce or r/ w . 7. this parameter is guaranteed by device characterization, but is not production tested. transition is measured 0mv from steady state with the output test load (figure 1). 8. if oe = v il during r /w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe = v ih during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . t ew must be met for either condition. ce = v il when ce 0 = v il and ce 1 = v ih . ce = v ih when ce 0 = v ih and/or ce 1 = v il . r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in (6) (4) (4) (7) be n 5632 drw 10 (9) ce or sem (9) (7) (3) . (7) 5632 drw 11 t wc t as t wr t dw t dh address data in r/ w t aw t ew be n (3) (2) (6) ce or sem (9) (9) . .
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 14 rapidwrite mode write cycle unlike other vendors' asynchronous random access memories, the idt70t651/9 is capable of performing multiple back-to-back write operations without having to pulse the r/ w , ce , or be n signals high during address transitions. this rapidwrite mode functionality allows the system designer to achieve optimum back-to-back write cycle performance without the difficult task of generating narrow reset pulses every cycle, simplifying system design and reducing time to market. during this new rapidwrite mode, the end of the write cycle is now defined by the ending address transition, instead of the r/ w or ce or be n transition to the inactive state. r/ w , ce , and be n can be held active throughout the address transition between write cycles. care must be taken to still meet the write cycle time (t wc ), the time in which the address inputs must be stable. input data setup and hold times (t dw and t dh ) will now be referenced to the ending address transition. in this rapidwrite mode the i/o will remain in the input mode for the duration of the operations due to r/ w being held low. all standard write cycle specifications must be adhered to. however, t as and t wr are only applicable when switching between read and write operations. also, there are two additional conditions on the address inputs that must also be met to ensure correct address controlled writes. these specifications, the allowable address skew (t aas ) and the address rise/fall time (t arf ), must be met to use the rapidwrite mode. if these conditions are not met there is the potential for inadvertent write operations at random intermediate locations as the device transitions between the desired write addresses. 5632 drw 08 t wc t wc t wc t ew t wp t wz t dh t dw t dw t dw t ow t wr address ce or sem (6) be n r/ w data in data out (2) (5) (5) t dh t dh (4) timing waveform of write cycle no. 3, rapidwrite mode write cycle (1,3) notes: 1. oe = v il for this timing waveform as shown. oe may equal v ih with same write functionality; i/o would then always be in high-z state. 2. a write occurs during the overlap (t ew or t wp ) of a ce = v il, be n = v il , and a r/ w = v il for memory array writing cycle. the last transition low of ce , be n, and r/ w initiates the write sequence. the first transition high of ce , be n, and r/ w terminates the write sequence. 3. if the ce or sem = v il transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 4. the timing represented in this cycle can be repeated multiple times to execute sequential rapidwrite mode writes. 5. this parameter is guaranteed by device characterization, but is not production tested. transition is measured 0mv from steady state with the output test load (figure 1). 6. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . t ew must be met for either condition. ce = v il when ce 0 = v il and ce 1 = v ih . ce = v ih when ce 0 = v ih and/or ce 1 = v il .
15 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges ac electrical characteristics over the operating temperature range and supply voltage range f or rapidwrite mode write cycle (1) symbol parameter min max unit t aas allowable address skew for rapidwrite mode ____ 1ns t arf address rise/fall time for rapidwrite mode 1.5 ____ v/ns 5632 tbl 14 note: 1. timing applies to all speed grades when utilizing the rapidwrite mode write cycle. timing waveform of address inputs for rapidwrite mode write cycle 5632 drw 09 a 0 a 17 t aas t arf t arf (1) note: 1. a 16 for idt70t659.
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 16 timing waveform of semaphore read after write timing, either side (1) notes: 1. d or = d ol = v il , ce l = ce r = v ih . refer to truth table ii for appropriate be controls. 2. all timing is the same for left and right ports. port "a" may be either left or right port. "b" is the opposite from port "a" . 3. this parameter is measured from r/ w "a" or sem "a" going high to r/ w "b" or sem "b" going high. 4. if t sps is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be gra nted the semaphore flag. timing waveform of semaphore write contention (1,3,4) notes: 1. ce 0 = v ih and ce 1 = v il are required for the duration of both the write cycle and the read cycle waveforms shown above. refer to truth table ii for de tails and for appropriate be n controls. 2. "data out valid" represents all i/o's (i/o 0 - i/o 35 ) equal to the semaphore value. sem (1) 5632 drw 12 t aw t ew i/o valid address t saa r/ w t wr t oh t ace valid address data valid in data out t dw t wp t dh t as t swrd t soe read cycle write cycle a 0 -a 2 oe valid (2) t sop t sop . sem "a" 5632 drw 13 t sps match r/ w "a" match a 0"a" -a 2"a" side "a" (2) sem "b" r/ w "b" a 0"b" -a 2"b" side "b" (2) .
17 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges notes: 1. port-to-port delay through ram cells from writing port to reading port, refer to "timing waveform of write with port-to-port read and busy (m/ s = v ih )". 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of the max. spec, t wdd ? t wp (actual), or t ddd ? t dw (actual). 4. to ensure that the write cycle is inhibited on port "b" during contention on port "a". 5. to ensure that a write cycle is completed on port "b" after contention on port "a". 6. 8ns commercial and 10ns industrial speed grades are available in bf-208 and bc-256 packages only. ac electrical characteristics over the operating temperature and supply voltage range symbol parameter 70t651/9s8 (6) com'l only 70t651/9s10 com'l & ind (6) 70t651/9s12 com'l & ind 70t651/9s15 com'l only unit min. max. min. max. min. max. min. max. busy timing (m/ s =v ih ) t baa busy access time from address match ____ 8 ____ 10 ____ 12 ____ 15 ns t bda busy disable time from address not matched ____ 8 ____ 10 ____ 12 ____ 15 ns t bac busy access time from chip enable low ____ 8 ____ 10 ____ 12 ____ 15 ns t bdc busy disable time from chip enable high ____ 8 ____ 10 ____ 12 ____ 15 ns t aps arbitration priority set-up time (2) 2.5 ____ 2.5 ____ 2.5 ____ 2.5 ____ ns t bdd busy disable to valid data (3) ____ 8 ____ 10 ____ 12 ____ 15 ns t wh write hold after busy (5) 6 ____ 7 ____ 9 ____ 12 ____ ns busy timing (m/ s =v il ) t wb busy input to write (4) 0 ____ 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (5) 6 ____ 7 ____ 9 ____ 12 ____ ns port-to-port delay timing t wdd write pulse to data delay (1) ____ 12 ____ 14 ____ 16 ____ 20 ns t ddd write data valid to re ad data de lay (1) ____ 12 ____ 14 ____ 16 ____ 20 ns 5632 tbl 15 symbol parameter 70t651/9s8 (4) com'l only 70t651/9s10 com'l & ind (4) 70t651/9s12 com'l & ind 70t651/9s15 com'l only min. max. min. max. min. max. min. max. sleep mode timing (zzx=v ih ) t zzs sleep mode set time 8 ____ 10 ____ 12 ____ 15 ____ t zzr sleep mode reset time 8 ____ 10 ____ 12 ____ 15 ____ t zzpd sleep mode power down time (5) 8 ____ 10 ____ 12 ____ 15 ____ t zzpu sleep mode power up time (5) ____ 0 ____ 0 ____ 0 ____ 0 5632 tbl 15a ac electrical characteristics over the operating temperature and supply voltage range (1,2,3) notes: 1. timing is the same for both ports. 2. the sleep mode pin shuts off all dynamic inputs, except jtag inputs, when asserted. optx, int x, m/ s and the sleep mode pins themselves (zzx) are not affected during sleep mode. it is recommended that boundary scan not be operated during sleep mode. 3. these values are valid regardless of the power supply level selected for i/o and control signals (3.3v/2.5v). see page 6 for details. 4. 8ns commercial and 10ns industrial speed grades are available in bf-208 and bc-256 packages only. 5. this parameter is guaranteed by device characterization, but is not production tested.
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 18 timing waveform of write with port-to-port read and busy (m/ s = v ih ) (2,4,5) timing waveform of write with busy (m/ s = v il ) notes: 1. t wh must be met for both busy input (slave) and output (master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 3. t wb only applies to the slave mode. notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for m/ s = v il (slave). 2. ce 0l = ce 0r = v il ; ce 1l = ce 1r = v ih . 3. oe = v il for the reading port. 4. if m/ s = v il (slave), busy is an input. then for this example busy "a" = v ih and busy "b" input is shown above. 5. all timing is the same for left and right ports. port "a" may be either the left or right port. port "b" is the port opposite from port "a". 5632 drw 14 t dw t aps addr "a" t wc data out "b" match t wp r/ w "a" data in "a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (3) t wdd t baa . 5632 drw 15 r/ w "a" busy "b" t wb (3) r/ w "b" t wh (1) (2) t wp .
19 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges ac electrical characteristics over the operating temperature and supply voltage range (1,2) waveform of busy arbitration controlled by ce timing (m/ s = v ih ) (1) waveform of busy arbitration cycle controlled by address match timing (m/ s = v ih ) (1,3,4) notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from port ?a?. 2. if t aps is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. 3. ce x = v il when ce 0 x = v il and ce 1 x = v ih . ce x = v ih when ce 0 x = v ih and/or ce 1 x = v il . 4. ce 0 x = oe x = be n x = v il . ce 1 x = v ih . 5632 drw 16 addr "a" and "b" addresses match ce "a" ce "b" busy "b" t aps t bac t bdc (2) . 5632 drw 17 addr "a" address "n" addr "b" busy "b" t aps t baa t bda (2) matching address "n" , 70t651/9s8 (3) com'l only 70t651/9s10 com'l & ind (3) 70t651/9s12 com'l & ind 70t651/9s15 com'l only symbol parameter min.max.min.max.min.max.min.max.unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t ins interrupt set time ____ 8 ____ 10 ____ 12 ____ 15 ns t inr interrupt reset time ____ 8 ____ 10 ____ 12 ____ 15 ns 5632 tbl 16 notes: 1. timing is the same for both ports. 2. these values are valid regardless of the power supply level selected for i/o and control signals (3.3v/2.5v). see page 6 for details. 3. 8ns commercial and 10ns industrial speed grades are available in bf-208 and bc-256 packages only.
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 20 truth table iii ? interrupt flag (1,4) waveform of interrupt timing (1) notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from port ?a?. 2. refer to interrupt truth table. 3. ce x = v il means ce 0 x = v il and ce 1 x = v ih . ce x = v ih means ce 0 x = v ih and/or ce 1 x = v il . 4. timing depends on which enable signal ( ce or r/ w ) is asserted last. 5. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. notes: 1. assumes busy l = busy r =v ih . ce 0 x = v il and ce 1 x = v ih . 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. int l and int r must be initialized at power-up. 5. a 17x is a nc for idt70t659. therefore, interrupt addresses are 1ffff and 1fffe. 5632 drw 18 addr "a" interrupt set address ce "a" (3) r/ w "a" t as t wc t wr (4) (5) t ins (4) int "b" (2) . 5632 drw 19 addr "b" interrupt clear address ce "b" (3) oe "b" t as t rc (4) t inr (4) int "b" (2) . left port right port function r/ w l ce l oe l a 17l -a 0l (5) int l r/ w r ce r oe r a 17r -a 0r (5) int r l l x 3ffff xxxx x l (2) set right int r flag xxxxxxll3ffffh (3) reset right int r flag xxx x l (3) l l x 3fffe x set left int l flag x l l 3fffe h (2) x x x x x reset left int l flag 5632 tbl 17
21 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges functional description the idt70t651/9 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt70t651/9 has an automatic power down feature controlled by ce . the ce 0 and ce 1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = high). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 3fffe (hex), where a write is defined as ce r = r/ w r = v il per the truth table. the left port clears the interrupt through access of address location 3fffe when ce l = oe l = v il , r/ w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 3ffff (hex) and to clear the interrupt flag ( int r ), the right port must read the memory location 3ffff. the message (36 bits) at 3fffe or 3ffff (1ffff or 1fffe for idt70t659) is user-defined since it is an addressable sram location. if the interrupt function is not used, address locations 3fffe and 3ffff are not used truth table iv ? address busy arbitration notes: 1. pins busy l and busy r are both outputs when the part is configured as a master. both are inputs when configured as a slave. busy outputs on the idt70t651/9 are push-pull, not open drain outputs. on slaves the busy input internally inhibits writes. 2. "l" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "h" if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. 4. a 17 is a nc for idt70t659. address comparison will be for a 0 - a 16 . 5. ce x = l means ce 0 x = v il and ce 1 x = v ih . ce x = h means ce 0 x = v ih and/or ce 1 x = v il . inputs outputs function ce l (5) ce r (5) a ol -a 17l (4) a or -a 17r busy l (1) busy r (1) x x no match h h normal hx match h h normal xh match h h normal ll match (2) (2) write inhibit (3) 5632 tbl 18 truth table v ? example of semaphore procurement sequence (1,2,3) notes: 1. this table denotes a sequence of events for only one of the eight semaphores on the idt70t651/9. 2. there are eight semaphore flags written to via i/o 0 and read from all i/o's (i/o 0 -i/o 35 ). these eight semaphores are addressed by a 0 - a 2 . 3. ce = v ih , sem = v il to access the semaphores. refer to the semaphore read/write control truth table. functions d 0 - d 35 left d 0 - d 35 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free 5632 tbl 19
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 22 busy logic busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applications. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the m/ s pin. once in slave mode the busy pin operates solely as a write inhibit input pin. normal operation can be programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt70t651/9 ram in master mode, are push-pull type outputs and do not require pull up resistors to operate. the busy arbitration on a master is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with the r/ w signal. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. semaphores the idt70t651/9 is an extremely fast dual-port 256/128k x 36 cmos static ram with an additional 8 address locations dedicated to binary semaphore flags. these flags allow either processor on the left or right side of the dual-port ram to claim a privilege over the other processor for functions defined by the system designer?s software. as an ex- ample, the semaphore can be used by one processor to inhibit the other from accessing a portion of the dual-port ram or any other shared resource. the dual-port ram features a fast access time, with both ports being completely independent of each other. this means that the activity on the left port in no way slows the access time of the right port. both ports are identical in function to standard cmos static ram and can be read from or written to at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous read/write of, a non-semaphore location. semaphores are pro- tected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the dual-port ram. these devices have an automatic power-down feature controlled by ce 0 and ce 1 , the dual-port ram chip enables, and sem , the semaphore enable. the ce 0 , ce 1 , and sem pins control on- chip power down circuitry that permits the respective port to go into standby mode when not selected. systems which can best use the idt70t651/9 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. these systems can benefit from a performance increase offered by the idt70t651/9s hardware semaphores, which provide a lockout mechanism without requiring complex programming. software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. the idt70t651/9 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. an advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. this can prove to be a major advantage in very high-speed systems. how the semaphore flags work the semaphore logic is a set of eight latches which are indepen- dent of the dual-port ram. these latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphores provide a hardware assist for a use assignment method called ?token passing allocation.? in this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. if the left processor wants to use this resource, it requests the token by setting the latch. this processor then if these rams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate. width expansion with busy logic master/slave arrays when expanding an idt70t651/9 ram array in width while using busy logic, one master part is used to decide which side of the rams array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master use the busy signal as a write inhibit signal. thus on the idt70t651/9 ram the busy pin is an output if the part is used as a master (m/ s pin = v ih ), and the busy pin is an input if the part used as a slave (m/ s pin = v il ) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. figure 3. busy and chip enable routing for both width and depth expansion with idt70t651/9 dual-port rams. 5632 drw 20 master dual port ram busy r ce 0 master dual port ram busy r slave dual port ram busy r slave dual port ram busy r ce 1 ce 1 ce 0 a 18 busy l busy l busy l busy l . as mail boxes, but as part of the random access memory. refer to truth table iii for the interrupt operation.
23 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges verifies its success in setting the latch by reading it. if it was successful, it proceeds to assume control over the shared resource. if it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. the left processor can then either repeatedly request that semaphore?s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. once the right side has relinquished the token, the left side should succeed in gaining control. the semaphore flags are active low. a token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. the eight semaphore flags reside within the idt70t651/9 in a separate memory space from the dual-port ram. this address space is accessed by placing a low input on the sem pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, ce 0 , ce 1 ,r/ w and be n) as they would be used in accessing a standard static ram. each of the flags has a unique address which can be accessed by either side through address pins a 0 ? a 2 . when accessing the semaphores, none of the other address pins has any effect. when writing to a semaphore, only data pin d 0 is used. if a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see truth table v). that semaphore can now only be modified by the side showing the zero. when a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. the fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (a thorough discussion on the use of this feature follows shortly.) a zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. when a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros for a semaphore read, the sem , be n, and oe signals need to be active. (please refer to truth table ii). furthermore, the read value is latched into one side?s output register when that side's semaphore select ( sem , be n) and output enable ( oe ) signals go active. this serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. a sequence write/read must be used by the semaphore in order to guarantee that no system level contention will occur. a processor requests access to shared resources by attempting to write a zero into a semaphore location. if the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see table v). as an example, assume a processor writes a zero to the left port at a free semaphore location. on a subsequent read, the processor will verify that it has written success- fully to that location and will assume control over the resource in question. meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. had a sequence of read/write been used instead, system contention problems could have occurred during the gap between the read and write cycles. it is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. the reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in figure 4. two semaphore request latches feed into a semaphore flag. whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. this condition will continue until a one is written to the same semaphore request latch. if the opposite side semaphore request latch has been written to zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first request latch. the opposite side flag will now stay low until its semaphore request latch is written to a one. from this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. the critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. the semaphore logic is specially designed to resolve this problem. if simultaneous requests are made, the logic guarantees that only one side receives the token. if one side is earlier than the other in making the request, the first side to make the request will receive the token. if both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. one caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. as with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. since any sema- phore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. figure 4. idt70t651/9 semaphore logic d 5632 drw 21 0 d q write d 0 d q write semaphore request flip flop semaphore request flip flop lport rport semaphore read semaphore read
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 24 timing waveform of sleep mode (1,2) notes: 1. ce 1 = v ih. 2. all timing is same for left and right ports. i z z i d d 5 6 3 2 d r w 2 2 , z z t z z p d c e 0 d a t a v a l i d a d d r e s s t z z r n o n e w r e a d s o r w r i t e s a l l o w e d n o r m a l o p e r a t i o n n o r m a l o p e r a t i o n s l e e p m o d e n o r e a d s o r w r i t e s a l l o w e d v a l i d d a t a a d d r e s s t z z s t z z p u
25 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges jtag ac electrical characteristics (1,2,3,4,5) 70t651/9 symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 3 (1) ns t jf jtag clock fall time ____ 3 (1) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 25 ns t jdc jtag data output hold 0 ____ ns t js jtag setup 15 ____ ns t jh jtag hold 15 ____ ns 5632 tbl 20 notes: 1. guaranteed by design. 2. 30pf loading on external output signals. 3. refer to ac electrical test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. 5. jtag cannot be tested in sleep mode. jtag timing specifications tck device inputs (1) / tdi/tms device outputs (2) / tdo trst t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch 5632 drw 23 x notes: 1. device inputs = all device inputs except tdi, tms, tck and trst . 2. device outputs = all device outputs except tdo. sleep mode the idt70t651/9 is equipped with an optional sleep or low power mode on both ports. the sleep mode pin on both ports is active high. during normal operation, the zz pin is pulled low. when zz is pulled high, the port will enter sleep mode where it will meet lowest possible power conditions. the sleep mode timing diagram shows the modes of operation: normal operation, no read/write allowed and sleep mode. for a period of time prior to sleep mode and after recovering from sleep mode (t zzs and t zzr ), new reads or writes are not allowed. if a write or read operation occurs during these periods, the memory array may be corrupted. validity of data out from the ram cannot be guaranteed immediately after zz is asserted (prior to being in sleep). during sleep mode the ram automatically deselects itself. the ram disconnects its internal buffer. all outputs will remain in high-z state while in sleep mode. all inputs are allowed to toggle. the ram will not be selected and will not perform any reads or writes.
idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature range s 26 identification register definitions instruction field value description revision number (31:28) 0x0 reserved for version number idt device id (27:12) 0x338 (1) defines idt part number 70t651 idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 indicates the presence of an id register 5632 tbl 21 scan register sizes register name bit size instruction (ir) 4 bypass (byr) 1 id entific atio n (idr) 32 boundary scan (bsr) note (3) 5632 tbl 22 note: 1. device id for idt70t659 is 0x339. system interface parameters instruction code description extest 0000 forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan register (bsr) between tdi and tdo. bypass 1111 places the bypass register (byr) between tdi and tdo. idcode 0010 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. highz 0100 places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. clamp 0011 uses byr. forces contents of the boundary scan cells onto the device outputs. places the bypass register (byr) between tdi and tdo. sample/preload 0001 places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2) and outputs (1) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. reserved all other codes several combinations are reserved. do not use codes other than those id entifie d ab ov e. 5632 tbl 23 notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, tck and trst . 3. the boundary scan descriptive language (bsdl) file for this device is available on the idt website (www.idt.com), or by conta cting your local idt sales representative.
27 idt70t651/9s preliminary high-speed 2.5v 256/128k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges ordering information a power 999 speed a package a process/ temperature range blank i commercial (0 cto+70 c) industrial (-40 cto+85 c) s standard power xxxxx device type idt s peed in nanoseconds . 70t651 70t659 9mbit (256k x 36) asynchronous dual-port ram 4mbit (128k x 36) asynchronous dual-port ram 256-ball bga (bc-256) 208-pin pqfp (dr-208) 208-ball fpbga (bf-208) bc dr bf 5632 drw 24 8 10 12 15 commercial only (1) commercial & industrial (1) commercial & industrial commercial only the idt logo is a registered trademark of integrated device technology, inc. preliminary datasheet: definition "preliminary' datasheets contain descriptions for products that are in early release. datasheet document history: 04/25/03: initial datasheet 10/01/03: page 9 added 8ns speed dc power numbers to dc electrical characteristics table page 9 updated dc power numbers for 10, 12 & 15ns speeds in the dc electrical characteristics table page 9, 11, 15, 17 & 25 added footnote that indicates that 8ns speed is available in bf-208 and bc-256 packages only page 10 added capacitance derating drawing page 11, 15 & 17 added 8ns ac timing numbers to the ac electrical characteristics tables page 11 added t soe and t lzob to the ac read cycle electrical characteristics table page 12 added t lzob to the waveform of read cycles drawing page 14 added t soe to timing waveform of semaphore read after write timing, either side drawing page 1 & 25 added 8ns speed grade and 10ns i-temp to features and to ordering information page 1, 14 & 15 added rapidwrite mode write cycle text and waveforms 10/20/03: page 15 corrected t arf to 1.5v/ns min. corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com note: 1. 8ns commercial and 10ns industrial speed grades are available in bf-208 and bc-256 packages only.

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